My client, a leader in their field, are looking for a Senior & Principal Physical Design engineer to come and work with them on either a contract, or permanent basis.
Working hybrid, out of either Oxford or Bristol, candidates will be asked to work on state of the art ASIC Development.
Applicants should be able to demonstrate the following skills:
- Solid hands-on experience with either Synopsys ICC* or Cadence Innovus for block-level and (ideally) full-chip design, ideally down to 16FF or below
- STA and timing closure, including constraint development and verification
- Power-management implementation using UPF/CPF, including verification and power estimation
- Power-rail analysis and verification
- Setup and use of RC extraction flows
- Ability to setup and run DRC/LVS/ERC/DFM using either Mentor or Synopsys tools
This role is available for an immediate start, although the client will wait for the right applicants notice period.
You must have the right to work on the UK to apply for this job.
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